Forum Discussion
Occasional ContributorAgilex 3 PLL in Source Synchronous mode ?
Regular ContributorHi BCuze,
Thank you for the follow-up, and sorry for the delay.
With the RGMII RxClock fixed on AT9, Quartus is reporting:
Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to <IOPLL>. Promote refclk to a global clock or use a dedicated IOPLL refclk pin.
That means AT9 is entering the clock network as a cluster clock resource, and there is no legal dedicated refclk route from that pin to an IOPLL location that can satisfy your placement. This is a device pin / clock-connectivity constraint, not a tool misconfiguration that can be overridden while keeping AT9 and source-synchronous compensation.
So, the specific assignment “AT9 drives an IOPLL in Source Synchronous compensation mode” is not workable on this pinout, which matches what we see when Quartus is allowed to pick a different clock pin (placement succeeds) versus when AT9 is forced (placement fails). Pin AT9 located in Bank 6E, which is an HVIO bank. The Agilex 3 Clocking and PLL User Guide (847921) states that the fabric-feeding PLL in HVIO banks 6E, 6F/6G, and 6H does not support compensation mode. Source synchronous is a compensation mode. That is why the Agilex 5 kit scheme does not port to this Atum A3 pinout.
It means this source-synchronous IOPLL from AT9 pin cannot be closed the way it was on the previous Agilex 5 kit. It does not by itself prove that Ethernet on the board is impossible under every architecture.
Can you share the board schematic? I will try to check if there are any other possible ways to solve this. Also, can you confirm you are using the kit below?
https://www.digikey.my/en/products/detail/terasic-inc/P0803/26766123
Regards,
Aqid
Occasional ContributorHi Aqid,
Yes, I confirm again that the Atum A3 nano is the Terasic board we're trying to use.
Terasic didn't want to share the complete schematics, even if we are a distributor, but we got some pages and the details about the PHY details including the bootstrap settings (RX[2:0]=100, TX[2:0]=100).
The pinout is what we used and it fails. Having access to the PHY MDIO doesn't help..
The PHY is using HVIOs : not smart...
As I explained, we found no way to close the RGMII timings on the Intel Agilex 5 kit other than using the PLL in Source Synchronous mode.
Hence the conclusion that the Atum A3 nano FPGA Eth PHY cannot be used (reliably or at all). It's a board design mistake (anyway, IMO, choosing RGMII is a poor choice since Cyclone V).
The only FPGA feature that could be demonstrated on the Atum A3 board seems to be the MIPI link (tbv).
- AqidAyman_Altera
Yes, I agree that for this board, the validated RGMII Gigabit Ethernet through a source-synchronous IOPLL is not available with the current pinout. Remaining options on this kit are limited to whatever Terasic documents for their Ethernet example (if they provide that), or other interfaces that are actually brought out, such as MIPI as you noted.
