Forum Discussion
Occasional ContributorAgilex 3 PLL in Source Synchronous mode ?
Regular ContributorHi Bert,
Please check your inbox.
I have reach out to you r4egarding this.
Regards,
Aqid
Occasional ContributorHi,
Letting Quartus select a suitable clock input pin does remove the error, sure...
But the problem is that we need actually to drive a PLL in Source synchronous mode by pin AT9 (1.8V LVCMOS).* This is not an option ! It is the Terasic Atum A3 nano board, and this scheme is the only way to reach timing convergence on the RGMII PHY (RxClock / RxData).
This scheme works on the Intel Agilex 5 kit.
We cannot ask Terasic to redo the board layout.
What do you suggest ?
* : note that the exact pin we need is AT9. We had to ask to get some schematics of the GBEth section.
The error message is :
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 IOPLL, which is within IOPLL IP pll_altera_iopll_2110_hws7ggy.
Info (14596): Information about the failing component(s):
Info (175028): The IOPLL name(s): u_pll|iopll_0|tennm_ph2_iopll
Error (16234): No legal location could be found out of 5 considered location(s). Reasons why each location could not be used are summarized below:
Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to "u_pll|iopll_0|tennm_ph2_iopll". Promote refclk to a global clock or use a dedicated IOPLL refclk pin. (4 locations affected)
Info (175029): IOPLL_X106_Y53_N346
Info (175029): IOPLL_X121_Y31_N846
Info (175029): IOPLL_X106_Y2_N346
Info (175029): IOPLL_X1_Y3_N346
Error (175006): There is no routing connectivity between the IOPLL and the IOPLL
Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 1 location affected
Info (175029): IOPLL_X121_Y6_N846
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
- AqidAyman_Altera
Hi,
I am able to get the design compiled successfully by letting Quartus selecting the clock input pin. You need to remove the I/O standard assigned first. Unfortunately, the compilation is failed if I assigned to the specific pin you mentioned (AT9).
Unless, if you promote it as a global clock, then the compilation is passed.
Below settings in .qsf in your project file:
set_location_assignment PIN_AT9 -to CLOCK0_50 -comment IOBANK_6E
set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to CLOCK0_50 -entity pll_bug
set_instance_assignment -name GLOBAL_SIGNAL ON -to CLOCK0_50Regards,
Aqid
- BCuze
Sure... but inserting a global buffer in front of a PLL in Source Synchronous mode just doesn't have a chance to achieve timing convergence. I am even surprised that Quartus allows this (it can't work).
The result is attached in the screen shot : -4 ns Hold Violation. No surprise.
The only conclusion we reach is that it is impossible on the Atum-A3-nano Terasic board to implement a validated RGMII interface. We succeeded on the Agilex 5 Intel kit (with lots of pain).
We strongly discourage Agilex users to go for RGMII (I am surprised after all these years that it is still attempted on modern boards). SGMII is certainly the solution (without sacrificing a transceiver, assuming the LVDS CDR work on A3 like it did on the old Cyclone 10 GX eg).
