AGIB027R29A1E2VC suppoprts LPO?

Hi, Looking at what's documented in the available sources, I can confirm the following about the 400G DR4 LPO demonstration on Agilex 7:

The demonstration is an interop demo implementing a **4x 100G design transmitting 400GbE traffic with 100G-DR4 LPO modules**, targeting Agilex 7 FPGAs and SoCs. Agilex™ 7 FPGAs and SoC FPGAs

For the specific hardware platform used in that type of testing, the **Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile)** — part number **AGIB027R31B1E1V** — is the documented hardware used for testing, along with an FMCA module for loopback. Triple-Speed Ethernet Intel Agilex™® 7 FPGA IP Design Example User Guide

On the transceiver tile side, the Agilex 7 I-Series uses F-Tile transceivers Agilex™ 7 FPGAs and SoCs Device Overview , and the Agilex 7 F-Tile supports a wide range of optical modules including XFP, QSFP-DD, OSFP, QSFP/QSFP28, QSFP56, SFP+, SFP28, SFP56, and CFP/CFP2/CFP4. Agilex™ 7 FPGAs and SoCs Device Overview

Regarding the media mode requirement for this type of design: for F-Tile FGT transceiver designs above 50G PAM4 using 400G optical modules for loopback, adaptation will fail unless the media mode is set to VSR/Optics. The workaround is to use the `set_media_mode` process in `ttk_helper_fgt_eth.tcl` to set media mode to VSR/Optics, following register-level steps for logical channels 0–15. This issue is fixed starting with **Quartus Prime Pro Edition Software version 22.3**. Why doesn’t my link come up when I use a 400G optical module in my Intel Agilex® 7 FPGA I-Series F-tile design?

So in summary: the FPGA board is the **Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile), AGIB027R31B1E1V**, running a 4×100G F-Tile FGT design with 100G-DR4 LPO modules to achieve 400GbE.