Addition Sum of Array

Hi phot,

When writing VHDL, you need to think about what logic will be synthesized, and what logic you're just using to make the code more readable.

In some cases, it makes the code easier to read and maintain by using tables and constants containing integers or real values. This works well, if those tables and constants are only used to initialize synthesizeable logic, eg., to initialize std_logic_vector signals or variables.

For example, look in the following example code for a linear feedback shift register. The code essentially uses the VHDL compiler to perform matrix operations, the results of which are then used to define hardware:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial_src.zip)

The adder_tree.vhd component in that source is what you would need to use if you were adding values together in a parallel operation.

If you were adding values from RAM, then you would only need one adder, and a clock per RAM location to read the data and then sum it. Keep in mind that your sum will have more bits than the input, so you need to make your adder as wide as needed to store the largest sum, eg., the sum of 100 8-bit values is ceil(log2(100)) = 7-bits wider (eg., 100 x FFh = 639Ch).

Cheers,

Dave