Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Addition Sum of Array

Hey @ all, i'm new here and i have some questions about the Sum of an array (VHDL), that contains a lot of 8 bit value's of std_logic_vector. For example i have declared the array as fol...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No, you cannot sum std_logic_vectors with standard VHDL. You can only perform arithmatic on unsigned or signed types. Std_logic_vectors are just an array of bits, so you have no idea if they are signed or unsigned or just a random bus.

So you need to convert them to signed or unsigned type first. You could easily write a function to sum the table. The question is, will vec_value always be a constant, or is it some kind of memory?