adding information regarding expected timing in the LPM_ADD_SUB section of the user guide

As I said in my original question, I am aware that there are many possible combinations and that it would be unrealistic to provide timing information relating to every single one of them. That is why, I suggested, that there should be timing information for only a select few combinations. This would still be helpful.

For example:

1. take only 2 of the most popular FPGA families
2. take only a single speed grade, neither the fastest, nor the slowest,
3. take the following implementation cases:
   • non-pipelined
   • pipelined, one-stage

The above, makes a total of 4 combinations, which is perfectly manageable.

For other IP cores, there is information, provided in the IP core's documentation, about the number of logic cells that would be required when instantiating the IP core in different FPGA families, together with a typical clock frequency that could be achieved.

I don't see any reason why the same analysis could not be done for the arithmetic cores and the results included in the documentation.