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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC Timing Constraints

I feel like I see this question over and over, but can't quite figure out the answer.

I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use to clock an ADC (ADS831). I sketched out a quick schematic showing what I'm talking about; the attached .gif. The Tcko on the ADC831 is 3.9-12 ns.

I've got the following constraints in my SDC file: 


create_generated_clock -name adc_clk -source   -divide_by 2 
#  ADC Input
set_input_delay -clock adc_clk -max 12.0 ] 
set_input_delay -clock adc_clk -min 3.9  ] 
set_multicycle_path -setup -end -from    -to   2
set_multicycle_path -hold  -end -from    -to   1

These constraints seem to be almost right, except I'm getting the always popular "Warning: No paths exist .... Assuming zero source clock latency." problem.

I've got Rysc's User Guide and Source-Synchronous Timing guides up, as well as the Timequest Cookbook and the API, and I've got to say I'm still stumped. Can anyone see what I'm missing here?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The principles are same; Timimg tool needs to know relation of ADC data relative to its clock (the clock that clocks its registers).

    if tCO of device is 3.9 ~ 12 ns then it tells the relation of data and ADC clock at device pins(not at fpga). if we assume there is 1 ns board delay for either data and ADC clock then ADC clock arrives 1 ns later at device, data is generated 3.9 ~ 12 ns from edge i.e. 4.9 ~ 13 ns with respect to fpga. Then data arrives at fpga 1 ns later i.e. relation now is 5.9 ~ 14 ns relative to ADC clock at fpga pins. However, ADC clock may not be the one that clocks data registers. The tool knows which clock to check and best practice is to fed correct set input delys then rotate PLL until you pass timing at data registers.