Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

ADC Timing Constraints

I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The principles are same; Timimg tool needs to know relation of ADC data relative to its clock (the clock that clocks its registers).

if tCO of device is 3.9 ~ 12 ns then it tells the relation of data and ADC clock at device pins(not at fpga). if we assume there is 1 ns board delay for either data and ADC clock then ADC clock arrives 1 ns later at device, data is generated 3.9 ~ 12 ns from edge i.e. 4.9 ~ 13 ns with respect to fpga. Then data arrives at fpga 1 ns later i.e. relation now is 5.9 ~ 14 ns relative to ADC clock at fpga pins. However, ADC clock may not be the one that clocks data registers. The tool knows which clock to check and best practice is to fed correct set input delys then rotate PLL until you pass timing at data registers.