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Altera_Forum
Honored Contributor
Honored ContributorADC Timing Constraints
I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_ForumHonored Contributor
Honored ContributorSampling analogue signal needs very good quality clock such as that from oscillators. Practically for low Fs like 62.5 a PLL inside fpga may do. But combinatorially generated clock is doubtful and its jitter will vary from build to build and with temperature...etc.
Secondly for your timing constraints remember that your adc clk is opposite in direction to data and you need to be careful about using equations for source synchronous case where data and clock go together.
