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Altera_Forum
Honored Contributor
Honored ContributorADC Timing Constraints
I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_ForumHonored Contributor
Honored ContributorPrimarily I haven't been using a PLL to generate ADC_CLK because I was trying to avoid adding extra things to the situation. Also I need to control the relationship between mc[0] and the ADC_CLK. That's resolvable, but it just seems to be adding more and more complexity to the problem. I was hoping for simple instead, since even with a PLL I'd need the tools to take into account the delay between the PLL and the actual PCB tracre.
