Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorADC Timing Constraints
I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_ForumHonored Contributor
Honored ContributorAs an aside note, why not use PLL since ADC clocked by your clock will suffer jitter and you may get around timing issues you have.
