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Altera_Forum
Honored Contributor
Honored ContributorADC Timing Constraints
I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_ForumHonored Contributor
Honored ContributorThe IO_BUF and CLKCTRL(this is just the global driver) should not cause any problems. I'm really not sure what the issue is. If you try it with a test design, does it work?
