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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC Timing Constraints

I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

CLK_125_IN goes through an IO_IBUF to become CLK_125_IN~input , then a CLKCTRL to become CLK_125_IN~inputclkctrl , both of which were inferred by the tools. I'm not quite sure what the difference between them is. (Architecture is an Arria II GX, by the way).

Interestingly enough, the adc_clk register is being clocked by CLK_125_IN~input, whereas practically everything else in the design, including mc[0], is being clocked by CLK_125_IN~inputclkctrl. I'm not quite sure what difference that makes, other than probably being the problem.