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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC Timing Constraints

I feel like I see this question over and over, but can't quite figure out the answer. I've got an 125 MHz clock coming in, from which I generate a 62.5 MHz clock using a TFF, which I then use ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Go to the technology map viewer and trace back from *mc*[0] to the source. Are you sure it's directly driven by CLK_125_IN, and that has a clock on it?

As you see, ADC_DATA is analyzed as it will make the generated clock, but it will be analyzed incorrectly, so definitely needs to be fixed.