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The said dynamic PLL dynamic phase shift feature is available for all Cyclone III - V FPGAs. It's a functionality you can use in your design, there's no ready-to-use IP block provided by Altera.
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really? that would be great!..is it called DPA (dynamic shift alignment) ? how do we activate this function? cause last time i check with altlvds_rx in Megawizard, it was grayed out, and someone in the forum said DPA is not available to Cyclone series.
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Synchronization of received data to your system clock may be an additional issue. In your initial example, you simply used the LVDS_RX output clock. This is convenient but mostly doesn't fir the design requirements.
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would you mind explaining further on this? can i use a DCFIFO to capture the parallel data? would it solve the problem?
Michael
Honored Contributor
