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I should add, the ADC i am working with, do comes with a bit clock (fast clock ) which is already 90 degree shifted for me. it is done inside the ADC. so i dont really need an extra PLL to phase shift it 90 degree.
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That's right. I assume, that the bitclock is just O.K. for the said 480 MBPS data rate. Near the Cyclone III speed limits, you may find an option to adjust the receiver phase helpful. This is much easier with a PLL.
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but it is only available in the CYCLONE 4 GX or Stratix, not CYCLONE 4 E
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The said dynamic PLL dynamic phase shift feature is available for all Cyclone III - V FPGAs. It's a functionality you can use in your design, there's no ready-to-use IP block provided by Altera.
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I want to use DDR format at the input and SDR at the output. i think it is done automatically by using altlvds_rx from the megawizard.
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Output from the LVDS_RX block is always SDR parallel data with the rate of the "slow clock" respectively frame clock.
Synchronization of received data to your system clock may be an additional issue. In your initial example, you simply used the LVDS_RX output clock. This is convenient but mostly doesn't fir the design requirements.
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