ADC output from LVDS deserializer.

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The other issue you haven't cleared is that do you use DDR IF and how to do convert it inside FPGA to SDR single data rate as this affects the clocking scheme you are using.

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I want to use DDR format at the input and SDR at the output. i think it is done automatically by using altlvds_rx from the megawizard. Attached is the table that i extracted from the user guide of altlvds_rx.

[J is the deserialization factor]

Michael