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I found out that, when i use lvds_rx core from megawizard, and set the phase shift to expect to be 90 degree.. everything works fine!! even without the timing constraint file above.
So i was wondering if the .SDC file is actually usefull here, so i made the phase shift to expect back to 0 degree, and with the contraint file.. the reconstructed wave will again appears to have lots of noise...
so it seems like the .SDC file does not do anything here.. i am confused, whats wrong with my timing constraint above?
Michael
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Sounds right to me. If you use LVDS_rx and it asks for data/clk relationship then I wonder why need sdc. Looks like timing control has two tier approach. Frankly I never came across any TimeQuest doc on such double tier timing control.
Obviously we have at least two areas which are timing critical, bit stream sampling at fpga using fast clock and parallel data sampling using data clock.
When you used lvds_rx I guess you also used its output clock for parallel data out instead of ADC frame clock (which is edge aligned with serial data). That should do the job. In that case I come to believe like you that simply use sdc for other than set input delay. In fact I will try set false path on all data/frame clk inputs and see what happens.
The other issue you haven't cleared is that do you use DDR IF and how to do convert it inside FPGA to SDR single data rate as this affects the clocking scheme you are using.
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