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The table doesn't directly specify data to frame clock relation. It tells implicitely, that frame clock and data are in phase, which is the case for other LVDS interface ADCs I've been working with (Analog and TI). This means, that the PLL must generate a phase shift of about 90° for the fast clock related to the frame clock to sample the data in the window center.
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I should add, the ADC i am working with, do comes with a bit clock (fast clock ) which is already 90 degree shifted for me. it is done inside the ADC.
so i dont really need an extra PLL to phase shift it 90 degree.
Michael
Honored Contributor
