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The table doesn't directly specify data to frame clock relation.
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yes .. you are right, this is something i've overlooked before i read the timing contraint cook book "Source Synchronous Timing with TimeQuest"written by Ryan Scoville aka rysc in this forum.
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You can't set this phase shift by timing constraints, it has to be set in the PLL parameters.
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are you sure ? are you sure i can't do it like this in the timing constraint? or do you mean the PLL output from ADC ?
create_clock -period 4.15 -name bitclk
create_clock -period 4.15 -name extbitclk -waveform {1.038 3.113}
derive_pll_clocks
derive_clock_uncertainty
set relationship 1.038 # these are from datasheet of TI's AFE5808
set adc_tsu 0.55
set adc_th 0.61
set adc_skew_max ;
set adc_skew_min ;
set board_data2clk_skew_max 0.05
set board_data2clk_skew_min -0.05
set TIADC_in_max ;
set TIADC_in_min ;
set_input_delay -clock extbitclk -max $TIADC_in_max }]
set_input_delay -clock extbitclk -min $TIADC_in_min }]
set_input_delay -clock extbitclk -max $TIADC_in_max }] -clock_fall -add_delay
set_input_delay -clock extbitclk -min $TIADC_in_min }] -clock_fall -add_delay
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Cyclone IV also offers an option to tune the phase automatically by utilizing the PLL dynamic phase shift feature.
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ya.. but it is only available in the CYCLONE 4 GX or Stratix, not CYCLONE 4 E
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It would be helpful, if you tell the actual ADC type.
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it is TI's AFE 5808 EVM, i just found out this is center aligned data lvds output(the bit clock and lvds data are 90 degree out of phase with each other)
I found out that, when i use lvds_rx core from megawizard, and set the phase shift to expect to be 90 degree.. everything works fine!! even without the timing constraint file above.
So i was wondering if the .SDC file is actually usefull here, so i made the phase shift to expect back to 0 degree, and with the contraint file.. the reconstructed wave will again appears to have lots of noise...
so it seems like the .SDC file does not do anything here.. i am confused, whats wrong with my timing constraint above?
Michael
Honored Contributor
