ADC output from LVDS deserializer.

The table doesn't directly specify data to frame clock relation. It tells implicitely, that frame clock and data are in phase, which is the case for other LVDS interface ADCs I've been working with (Analog and TI). This means, that the PLL must generate a phase shift of about 90° for the fast clock related to the frame clock to sample the data in the window center.

You can't set this phase shift by timing constraints, it has to be set in the PLL parameters. Personally, I prefer to adjust the phase shift parameter manually by centering it between the margins. (Apparently, you have already found one margin). But if you start with a reasonable value, the design can be expected to operate at moderate speeds.

Cyclone IV also offers an option to tune the phase automatically by utilizing the PLL dynamic phase shift feature. But I think, this is only meaningful for a design operating near the LVDS speed limit, where sampling windows are pretty small. And there's no ready made Altera IP for this purpose.

It would be helpful, if you tell the actual ADC type.

Regards,

Frank

P.S.: I didn't yet read your latest posts. The last shows that you are moving in the right direction, but the clock phase is still at the sampling window margin. Most likely, it has to be shifted just by 90 degree.