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Your sdc looks ok to me. Check report if you indeed got that.
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There is too much report data, i don't know where to look.
Is this the one i should be looking for ?
Info: Worst-case setup slack is 0.202
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.202 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]
Info: 3.436 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]
Info: 47.987 0.000 altera_reserved_tck
Info: Assembler is generating device programming files
Info: Worst-case hold slack is 0.160
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.160 0.000 altera_reserved_tck
Info: 0.162 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]
Info: 0.170 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]
Info: Worst-case recovery slack is 49.169
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 49.169 0.000 altera_reserved_tck
Info: Worst-case removal slack is 0.471
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.471 0.000 altera_reserved_tck
Info: Worst-case minimum pulse width slack is 1.251
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 1.251 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]
Info: 1.867 0.000 HSMC_CLKIN_P2
Info: 12.205 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]
Info: 49.285 0.000 altera_reserved_tck
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 18 warnings
Info: Peak virtual memory: 280 megabytes
Info: Processing ended: Sat Oct 15 19:37:28 2011
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 413 megabytes
Info: Processing ended: Sat Oct 15 19:37:29 2011
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Info: Quartus II Full Compilation was successful. 0 errors, 517 warnings
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If it is DDR, you will need constraints for both edges.
You can also try rotate the PLL clock if you are using pll if you can't pass timing.
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like this ?.
create_clock -period 4.15 [get_ports HSMC_CLKIN_P2]
create_clock -period 4.15 [get_ports HSMC_CLKIN_N2]
set_input_delay -clock HSMC_CLKIN_P2 -max 0.61 [get_ports HSMC_RX_D_P[11]]
set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [get_ports HSMC_RX_D_P[11]]
set_input_delay -clock HSMC_CLKIN_P2 -max 0.61 [get_ports HSMC_RX_D_N[11]]
set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [get_ports HSMC_RX_D_N[11]]
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Moreover, it could be timing not at io but at point when you sample the data on to 40MHz. Note 40MHs clock is edge aligned with data and you better do some shift away from edge e.g sample on opposite edge.
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I get what you mean, but how do i do "shifting away from the edge" ?
Thank you for your advice.
Michael
Honored Contributor
