Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

ADC interfacing code for 3-wire SPI using Verilog

Hi guys, I'm writing some Verilog code to interface a simple 12-bit serial ADC to an FPGA and I have some questions about my methodology. The ADC that I'm using is the ADS7818 from Texas Ins...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The delays can be predicted rather exactly for a known design structure. When CLK8 is sourced from the FPGA internally, the I/O delays effectively add to the ADC tco. I think, DATA should be sampled at the falling clock in this case.

If you want to visualize the timing, you can operate SignalTap at the 200 MHz system clock or the 32 MHz PLL clock and acquire the respective ADC signals at the pins.