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Altera_Forum
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16 years ago

ADC interfacing code for 3-wire SPI using Verilog

Hi guys, I'm writing some Verilog code to interface a simple 12-bit serial ADC to an FPGA and I have some questions about my methodology. The ADC that I'm using is the ADS7818 from Texas Ins...
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Altera_Forum
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16 years ago

Yes, the CONV input is sampled and DATA set at the CLK falling edge, so the SPI master should set/sample the signals at the rising edge. That's the standard method to operate SPI interfaces, except for high speeds. With ADS7818, the 30 to 50 ns tco of DATA nearly suggests to sample it at the next falling CLK edge. I would decide this depending on CLK8 generation method and possibly involved additional circuit delays.

If I counted right, D0 is present at DATA for (count == 13), so either data_temp should be sampled for (count == 14) or tmp[0] must be copied direct from serial input. Every thing else is perfect in jakobjones' suggestion, I think.