ADC interfacing code for 3-wire SPI using Verilog

Your thinking seems correct to me. Except I think you are off by a clock cycle (actually half a cycle). The ADC will drive data out on the falling edge of clock. If you sample on the negedge of cycle 1, you're going to get the active low data enable rather than the MSB of the data.

I really think you ought to be doing everything here on the rising edge. How are you driving the clock to the ADC? It appears you need a 10ns hold time from the falling edge of clock to conv. You need to ensure this occurs. Again, use the rising clock edge.

Consider the following:

//register declarations
    reg conv;
    reg rdy;
    reg  count;
    reg  data_temp;
    reg  tmp;
    
    //The clock counter. Starts at 0, so clock is from 0-15 instead of 1-16.
    always @ (posedge CLOCK_8)
        count <= count + 4'd1;
    
    //Assert the CONV signal
    always @ (posedge CLOCK_8)
        conv <= !&count;
    
    //Read the serial data into a 12-bit register. Afterwards, convert it to parallel if the count is 13 (end of data stream)
    always @ (posedge CLOCK_8)
        begin
                data_temp   <= {data_temp,serial_data]};
            if (count == 13)
                tmp <= data_temp;
        end