Hello, Does anyone know where the documentation/HDL instantitiation templates for the ADC Hard Block is located? I want to configure and access the ADC directly without using the modular adc IP. Thanks, - Sam

Hi Sam, Yes can instantiate using macros. Not recommenced. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

--- Quote Start --- Hi Sam, Yes can instantiate using macros. Not recommenced. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) --- Quote End --- Really not very helpful! have you read through the documentation? https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_adc.pdf

Hi Tricky, Let me know, if there is something wrong/missing anything. I have read that document, it explains "The Altera Modular ADC or Altera Modular Dual ADC IP core is a soft controller for the ADC hard IP blocks, we can generate soft IPs to instantiate the on-chip ADC blocks" But as per the question we need to instantiate the hard IP without using IP's. Using TCL/macros we can configure and instantiate it. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

--- Quote Start --- Hi Tricky, Let me know, if there is something wrong/missing anything. I have read that document, it explains "The Altera Modular ADC or Altera Modular Dual ADC IP core is a soft controller for the ADC hard IP blocks, we can generate soft IPs to instantiate the on-chip ADC blocks" But as per the question we need to instantiate the hard IP without using IP's. Using TCL/macros we can configure and instantiate it. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) --- Quote End --- Then why not show the OP how to do it?

I think the key line from the user guide is: --- Quote Start --- To create your ADC design, you must customize and generate the ALTPLL and Altera Modular ADC IP cores --- Quote End --- "must" is pretty clear to me. However if, using macros/tcl, there is a way of that suggests "must" actually means "don't have to", then I'd love to know how... Cheers, Alex

ADC Hard Block primitive | Altera Community

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Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Have you tried contacting Altera via mysupport? often, specific questions get you through directly to the correct support people, who can either provide the docs or tell you how to drive it.
--- Quote End ---

I will try that. Thanks.
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Refer to figure 8 in the ADC Timing section of the <DELTED>.

What you've instantiated there is essentially what results having configured the IP from the catalogue into 'Configuration 4: ADC Control Core Only'. Refer to section 2.2.1 "Altera Modular ADC IP Core Configuration Variants", in the same document.

Cheers,
Alex

Edit
**Sorry - need to acknowledge that's exactly what you said you did...
--- Quote End ---

For some reason I am having a hard time replying with a quote...
This isn't exactly correct. ADC Control Core Only does implement a FSM and FIFO to support the Avalon-ST command/control interface. I am really looking for information on the raw control signals to the ADC block.

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ADC Hard Block primitive

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