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Hi Kaz,
If I describe how I understand it, the virtual clock is the launch clock, which is latching the adc data at the adc. the latch clock is the clock received at the pin which is 90 degree shifted to make it center aligned. The relationship that I am describing in the sdcs should be from the rising edge of the launch to the rising edge of the latch as the data is output at the adc on that rising edge and should be valid to be latched by the rising edge received at the pin. vice versa with the falling edge. Changing the false paths means that I am saying the data is launched on the rising edge and should be valid at the faling edge of the received clock but that doesnt describe how the adc is outputting data and what I have in the design. (see 3rd image)
Does that make sense?
Regards
James
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virtual clock is the adc launch clock
fpga clock at the pin is shifted 90 degrees to indicate centre aligned data (instead of conventional delay figures)
Then we have two options to tell timequest: same edge transfer or opposite edge transfer. Both are correct as long as fpga is aware of it.
In the first case (your sdc) you are going for same edge then you found out that opposite edge is better which I expected and doesn't need pll as falling edge is centred on data eye launched by rising edge and rising edge is centre aligned on data eye launched by falling edge.
Now for the second case you need to tell fpga how to de-interlave ddr data as Hdata/Ldata are now reversed.
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