Achieving Timing Closure on Source Synchronous DDR Input

Hi Kaz,

I tried the first option, still had some timing failures, then tried the second option and it passed timing. (see attached setup3 and hold3)

It worked on my board but by changing the false paths it looks like it isnt correctly describing the waveform.

If I describe how I understand it, the virtual clock is the launch clock, which is latching the adc data at the adc. the latch clock is the clock received at the pin which is 90 degree shifted to make it center aligned. The relationship that I am describing in the sdcs should be from the rising edge of the launch to the rising edge of the latch as the data is output at the adc on that rising edge and should be valid to be latched by the rising edge received at the pin. vice versa with the falling edge. Changing the false paths means that I am saying the data is launched on the rising edge and should be valid at the faling edge of the received clock but that doesnt describe how the adc is outputting data and what I have in the design. (see 3rd image)

Does that make sense?

Regards

James