Achieving Timing Closure on Source Synchronous DDR Input

I will try first the easiest options:

# create virtual clock latching data @ source
create_clock -name vir_clk_adc    -period 4
# create clock that is received @ pin (90 degree shift)
create_clock -name clk_adc        -period 4 -waveform {1 3} 
derive_clock_uncertainty
#  set input constraint using setup and hold wrt virtual clock#  max = Tperiod/4 - Tsu#  min = Th - Tperiod/4
set_input_delay -clock vir_clk_adc -max 0.250   *}]
set_input_delay -clock vir_clk_adc -min -0.250   *}]
set_input_delay -clock vir_clk_adc -max 0.250   *}] -clock_fall -add_delay
set_input_delay -clock vir_clk_adc -min -0.250   *}] -clock_fall -add_delay
# false path double data rate edges
set_false_path -setup    -rise_from    {vir_clk_adc} -fall_to {clk_adc}
set_false_path -setup    -fall_from    {vir_clk_adc} -rise_to {clk_adc}
set_false_path -hold     -rise_from    {vir_clk_adc} -rise_to {clk_adc}
set_false_path -hold     -fall_from    {vir_clk_adc} -fall_to {clk_adc}

# create virtual clock latching data @ source
create_clock -name vir_clk_adc    -period 4
# create clock that is received @ pin (90 degree shift)
create_clock -name clk_adc        -period 4 -waveform {1 3} 
derive_clock_uncertainty
#  set input constraint using setup and hold wrt virtual clock#  max = Tperiod/4 - Tsu#  min = Th - Tperiod/4
set_input_delay -clock vir_clk_adc -max 0.250   *}]
set_input_delay -clock vir_clk_adc -min -0.250   *}]
set_input_delay -clock vir_clk_adc -max 0.250   *}] -clock_fall -add_delay
set_input_delay -clock vir_clk_adc -min -0.250   *}] -clock_fall -add_delay
# false path double data rate edges
set_false_path -setup    -rise_from    {vir_clk_adc} -rise_to {clk_adc}
set_false_path -setup    -fall_from    {vir_clk_adc} -fall_to {clk_adc}
set_false_path -hold     -rise_from    {vir_clk_adc} -fall_to {clk_adc}
set_false_path -hold     -fall_from    {vir_clk_adc} -rise_to {clk_adc}