Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Achieving Timing Closure on Source Synchronous DDR Input

Hi I am looking for some help achieving timing closure in a design. I am using a TI ADS4149 EVM Board and connecting it to a Terasic C5 SoC Dev Board. The ADC outputs Source Synchronous D...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

ADC data is input to FPGAs and its tSU/tH must be related to its own inputs unrelated to FPGA.

Your DDR is centre aligned and so best to use small skew range.

also try both ways of edge transfers(same edge and opposite edge). You may remove PLL for a start.