Achieving Timing Closure on Source Synchronous DDR Input

Hi Kaz,

I used tSU and tH as they were specified for the adc in the datasheet and I couldnt find a skew value. AN433 in section FPGA Centric Input Delay Constraints says you can use Unit interval (period/2 for DDR) and setup and hold values for the input delays : UI/2-tSU and tH-UI/2 for source sync inputs.

I hadnt played with the pll phase yet due to having both setup and hold delays, I understand that if I had positive setup slack then I could move it to get less negative hold slack and vice versa but with both already being negative i dont see how I can get them both to be positive!!

regards

James