Forum Discussion

Honored Contributor

11 years ago

Achieving Timing Closure on Source Synchronous DDR Input

Hi I am looking for some help achieving timing closure in a design. I am using a TI ADS4149 EVM Board and connecting it to a Terasic C5 SoC Dev Board. The ADC outputs Source Synchronous D...

multiple-attachments.zip886 KB

Altera_Forum

Honored Contributor

11 years ago

your sdc looks ok to me though I don't understand why tSU and tH are commented for calculation of delays. I expected a small skew range instead.

You have PLL phase to play with to get timing closure. Have you tried that?

Forum Discussion

Achieving Timing Closure on Source Synchronous DDR Input

Recent Discussions

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Operating temperature for 10M08DCF256A7G

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Download links not working

JTAG Chain Broken on Agilex 7-I Dev Kit