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Honored Contributor
Honored ContributorAchieving Timing Closure on Source Synchronous DDR Input
Hi I am looking for some help achieving timing closure in a design. I am using a TI ADS4149 EVM Board and connecting it to a Terasic C5 SoC Dev Board. The ADC outputs Source Synchronous D...
Altera_ForumHonored Contributor
Honored Contributoryour sdc looks ok to me though I don't understand why tSU and tH are commented for calculation of delays. I expected a small skew range instead.
You have PLL phase to play with to get timing closure. Have you tried that?
