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Honored Contributor
Honored ContributorACEX1k
Hello Guys I am using the ACEX 1k ALTERA with MAXPLUSII In my FPGA I have a 48Mhz clk, in some where I use the 48Mhz clk as input to a "CLKLOCK" block that make from this 48Mhz clk a 96Mhz clk, ...
Altera_ForumHonored Contributor
Honored ContributorClock tree is the pre-done, low skew routing tree that is done in the hardware to distrubute clocks throughout the device. In the Acex 1K family I think it only fed the clock ports of registers.
If you're clock rate is 96MHz, hence your data rate is 96MHz, why do you need a signal that transitions twice(one rising and one falling edge) per clock? Are you using negative edge registers, maybe doing a double-data rate application?
