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Altera_Forum
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19 years ago

ACEX1k

Hello Guys I am using the ACEX 1k ALTERA with MAXPLUSII In my FPGA I have a 48Mhz clk, in some where I use the 48Mhz clk as input to a "CLKLOCK" block that make from this 48Mhz clk a 96Mhz clk, ...
Altera_Forum's avatar
Altera_Forum
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19 years ago

Hey

first thanks for ur help but :

I do not think that i can use 196Mhz, this is not possible in ACEX 1K.

what is a clk tree ?

thanks

Amirster