Accelerate design performance

Ahhh... I've heard X recommends making resets synchronous, and this might finally explain why. A quick perusing of their document, and I think everything else holds true for Altera, but I do know Altera recommends an asynchronous reset for performance, sinc the asynchronous input is a dedicated input, and basically wasted if you make your reset synchronous. More importantly, the reset will now use a synchronous input that could have been used for synchronous logic.

In general, I strongly recommend using the aysnchronous assert/synchronous de-assert reset circuit. It uses the asynchronous input of the register. The way it's designed allows it to assert asynchronously, so if the system clock disappears the device can still be reset to a good state rather than being stuck in it's current state(useful if your design, say, controls the acceleration of a car). But it de-asserts synchronously insuring that every register in the domain comes out together and start toggling together every time out of reset(this is probably one of the main things I've seen people having to debug after shiiping product, recovery and removal failures.) This circuit is described in more detail at:

http://www.alteraforum.com/forum/showthread.php?t=5026&highlight=recovery