Honored Contributor
Honored ContributorThanks.
I understand the requirement for DC balance well and will make sure the data is encoded like that. I overcame my fear of electronics and played around with LTspice a bit. Square wave through a capacitor with a DC bias on the other side puts the square wave at the DC bias voltage on that side. so basically. the DC biases are separate on both sides. LVDS Tx has its own bias. 2.5V CML Rx has its own bias at. 1.4V Connecting both sides with a capacitor will only allow the transition of a DC balanced signal across. And not the bias. Vhigh-Vlow (differential signal) is similar for both LVDS and CML. Hence, connecting the two with a capacitor will work. Now the question remains which part.. http://pdfserv.maximintegrated.com/en/an/an292.pdf helps a bit.. 100nf ceramic capacitor. sizes 0402 and 0603. http://www.digikey.com/product-detail/en/c1005x5r1a104k050ba/445-1265-1-nd/567732 Will this work? Cheers Zubair
