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Altera_Forum
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11 years ago

AC coupled LVDS input internal DC bias for Cyclone V

Hi all, I have a board with Cyclone V GX device in which i give the LVDS 2.5V clock from oscillator to Clk1p and Clk1n pins of FPGA. I have AC coupled the clock input and i have simulat...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I have the same question for the Cyclone 10 LP series: Does it provide internal DC bias for the LVDS inputs (since it doesn't have dedicated transceivers, I will use the GPIOs in LVDS mode)?

I will connect it to a SGMII interface of a 1G Switch core, so I will need >700 Mbps data rates with AC coupling. For this speed the datasheet specifies a minimum common mode voltage (V_ICM) of 1.05 V. Should I need to add external resistor dividers for ~1.2 V DC biasing?

Thanks for your help in advance.