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Altera_Forum
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11 years ago

AC coupled LVDS input internal DC bias for Cyclone V

Hi all, I have a board with Cyclone V GX device in which i give the LVDS 2.5V clock from oscillator to Clk1p and Clk1n pins of FPGA. I have AC coupled the clock input and i have simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The good thing with internal DC bias when you enabled the RD is it helps to save the on board resistor networks. You can opt not to use the RD and build your own biasing resistor network as well on the board when use AC coupling. If you are using DC coupling, then you need to ensure the VCM of your link meet the LVDS receiver VICM specs to ensure it can function as expected and avoid damaging the receiver.