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Altera_Forum
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11 years ago

AC coupled LVDS input internal DC bias for Cyclone V

Hi all, I have a board with Cyclone V GX device in which i give the LVDS 2.5V clock from oscillator to Clk1p and Clk1n pins of FPGA. I have AC coupled the clock input and i have simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks genoli for your quick reply.

I had read this information before too but i was not sure if it is more like a requirement for coming singal ended signal or it is a Cyclone V provided DC Bias.

You mean that cyclone V provides 1.25VCM for all incoming LVDS P+ and N- signals ?

Sorry but i just want to confirm if i am reading the documentation correctly.

Thanks again.