Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorabout Tri-State Logic gate
i want to make a Tri-State Logic gate,but the putout is always high impedance .why here's my code； library ieee; use ieee.std_logic_1164.all; entity e is port( datain:in std_logic...
Altera_ForumHonored Contributor
Honored Contributoryou cannot read an out port, so there is no need to tri-state it. Because of that your logic got converted to a mux.
I am assuming you did a post compilation simulation, because you would have seen no problems with an RTL simulation (and then the differences between hardware and simulation would have caused you problems).
