Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorabout Tri-State Logic gate
i want to make a Tri-State Logic gate,but the putout is always high impedance .why here's my code； library ieee; use ieee.std_logic_1164.all; entity e is port( datain:in std_logic...
Altera_ForumHonored Contributor
Honored Contributordid you make dataout an inout port? it wont work as just an out port.
And is this an RTL simulation or post place and route?
