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Honored Contributor
Honored Contributorabout Tri-State Logic gate
i want to make a Tri-State Logic gate,but the putout is always high impedance .why here's my code； library ieee; use ieee.std_logic_1164.all; entity e is port( datain:in std_logic...
Altera_ForumHonored Contributor
Honored Contributorin simulation.but it's so strange.today i try again.when enable is 1,dataout is same as datain.but when enable is 0,dataout is always 0.so my question is changed.dose 0 stand for high impedance in quartus ii?
