About Transceiver???

Hi,

It seems to me that there is some confusion about serdes functionality.

Let us assume your serialisation ratio is 8. The receiver(serdes Rx) will recover both the bytes and the byte clock. You don't have to worry about data recovery, this is done for you by the serdes Rx. This means the serdes Rx deals with the nasty high speed work and gives you the data and its clock at a gentle speed(= link speed/8) suitable for processing inside the logic area of FPGA. This is so irrespective of data rate on the link as long as it is below the maximum link rate.

(Usually) it is your task is to align the byte boundary and lock to your stream before you can do any further processing. You also need to know when data is valid since it can be at any rate(serdes Rx wouldn't know that). The link itself will have a constant speed but data can be bursty. I mean, when you enter the link speed say 1Gbps then your data can be anything between zero~1G. Thus, there must be a protocol between you and the Tx to know when data is valid and when it is not. I don't see any relevance of upsampling in this context, please explain that if you wish.

Please note that devices are different and are changing continuously and may be your device will do things like byte-alignment automatically or even take over the task of stream detection/locking). My own experience was with stratix II and so may not exactly apply to your case in some details.

Regards

Kaz