About Transceiver???

Hi, Kaz, you are so kind, thank you for your help! May I ask you some more questions?

I'm clear that I can recover the clock from 1Gbps bursty input data through the transceiver.

You know, my last goal is to recover the input data after recovering the clock. When the data rate is only under 500Mbps, I can use the FPGA to recover the input data by the way of oversampling through recovered clock.

But when the data rate is 1Gbps, althogh I can get the recovered clock, limited by the internal working speed of the FPGA(always below 1GHz), it seems that I can't use the oversampling to recover the input data.

Can the transceiver not only recover the clock, but also recover the input data? If the transceiver can finish it, I think I can deserialize the recovered data, then deal with them by FPGA. If the transceiver can't reach that request, what should I do after recovering the clock for the goal of recovering the bursty 1Gbps input data?

There're some references on the internet about recovering data whose rate is over 1Gbps. But most of them are suggesting to design special circuit to fullfil the request, I think it's not easy for us to make that special circuit. So our idea is to find a good FPGA dev board to finish it. We can realize recovering 100Mbps bursty input data, but puzzled by 1Gbps. If the transceiver can solve the problem of recovering 1Gbps bursty input data, I think it will be our best choice now.

Hope for your help!