About Transceiver???

Generally speaking, Yes you can by using the "serdes" part available in some FPGAs and it works whether the stream is bursty or not as long as the link speed is not violated. Usually these serdes have multiple channels.

The serdes will need a suitable reference clock for its internal PLL. It will then recover the serial data into say bytes outputting also the byte clock.

You - the designer - will need extra work to lock to your stream and you will need to align the byte boundaries e.g. by using a state machine.

Additionally your board layout should accomodate the speed.

Practically, you need to instantiate a serdes receiver(and a transmitter if you are sending bytes as well). read its data sheet and once you done that then apply your lock/byte alignment algorithms to the byte stream which is output by the serdes rceiver. This should be done per channel if you are using more than one channel.

Locking to stream can be made easy by having the link send known patterns when idle(training pattern).

In case of serdes transmitter, just send your bytes across, it doesn't need any locking of course but you may send training patterns if the other receiver neds them. The receiver and transmiter may share the same reference clock.

Regards

Kaz