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Honored Contributor
Honored ContributorAbout Stratix4 IO feature
The Stratix4 handbook said the setup time of input pin is about 200ps. Does it means a signal about 3Gbps could pass through the IO pins in Stratix4 devices, and I can use plural clocks(300MHz) wi...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If you were going to implement a sigma-delta converter, then noise shaping requires converting the quantization noise signal back to analog. It sounds like you are just implementing a plain-old 1-bit ADC, so you do not have to worry about this comment. Are you using a clocked comparator? If you are not then all you are doing is converting the analog signal with arbitrary amplitude into a binary signal, i.e., a signal with only two voltage levels. You are performing amplitude quantization, but are not sampling the signal. When you sample the signal at the transceiver, you will generate setup/hold errors, since the transition of the binary signal is not synchronous. Cheers, Dave --- Quote End --- --- Quote Start --- Are you using a clocked comparator? --- Quote End --- As you said, not a clocked comparator. --- Quote Start --- you will generate setup/hold errors, since the transition of the binary signal is not synchronous. --- Quote End --- That would be inevitable to generate setup/hold errors, if I sample an arbitrary signal using transceiver. What I need to do is just sample. No information I should recovery from the input signal.
