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Honored Contributor
Honored ContributorAbout Stratix4 IO feature
The Stratix4 handbook said the setup time of input pin is about 200ps. Does it means a signal about 3Gbps could pass through the IO pins in Stratix4 devices, and I can use plural clocks(300MHz) wi...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- BTW, I do not need to converter the signal back to analog. --- Quote End --- If you were going to implement a sigma-delta converter, then noise shaping requires converting the quantization noise signal back to analog. It sounds like you are just implementing a plain-old 1-bit ADC, so you do not have to worry about this comment. --- Quote Start --- In my design, a high speed comparator convert the analog signal into a certain logic level, such as lvds, cml, lvpecl, etc. Then sample it every 400ps. At last the analog signal changes to a 2.5Gbps digital data, and I will analyze the digital data in FPGAs. --- Quote End --- Are you using a clocked comparator? If you are not then all you are doing is converting the analog signal with arbitrary amplitude into a binary signal, i.e., a signal with only two voltage levels. You are performing amplitude quantization, but are not sampling the signal. When you sample the signal at the transceiver, you will generate setup/hold errors, since the transition of the binary signal is not synchronous. Cheers, Dave
