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Ryan is correct, you can do this.
Its can be used to create a 1-bit high-speed ADC. You configure the XCVR in basic mode and implement manual control of the CDR lock-to-reference and lock-to-data control signal. Its not that great for creating a multi-channel ADC, since each receiver deserializer starts independently.
What types of signals are you planning on sampling? If you want to oversample, then you gain 1-bit (6dB ) for every 4x oversampling. How many bits (what dynamic range) do you need in your final signal? I don't think you can implement a sigma-delta converter, since you need to convert the signal back to analog, and there is an unknown delay in the receiver-back-to-transmitter path. You can do this with LVDS buffers. I think Altera has a MAX II app note that shows sigma-delta, and Lattice definitely has one.
Cheers,
Dave
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BTW, I do not need to converter the signal back to analog.
In my design, a high speed comparator convert the analog signal into a certain logic level, such as lvds, cml, lvpecl, etc. Then sample it every 400ps. At last the analog signal changes to a 2.5Gbps digital data, and I will analyze the digital data in FPGAs.
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