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Honored Contributor
Honored ContributorAbout Stratix4 IO feature
The Stratix4 handbook said the setup time of input pin is about 200ps. Does it means a signal about 3Gbps could pass through the IO pins in Stratix4 devices, and I can use plural clocks(300MHz) wi...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I don't think regular I/O are the way to go. 3Gbps just seems way too out there. Could you use a transceiver and just hold the CDR unit in "lock to ref" mode instead of lock to data? That way you're not really recovering a clock out of it? (I may be way off base, just throwing out an idea...) --- Quote End --- Hello Rysc!! i'm so glad to receive your answer above, because I had tried to use a transceiver,and lock its clock to ref clk. That method worked, but one deserialized channel cannot be sync well. For example, the deserializer factor is 10, all the deserialize channels synchronized to the slow clock, except the channel 5. The data on ch5 was asserted after the slow clock's rising edge(Tsu is negtive), the data on other channels was valid before the rising edge.
