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Altera_Forum
Honored Contributor
14 years agoAbout Stratix4 IO feature
The Stratix4 handbook said the setup time of input pin is about 200ps. Does it means a signal about 3Gbps could pass through the IO pins in Stratix4 devices, and I can use plural clocks(300MHz) wi...
Altera_Forum
Honored Contributor
14 years agoIs the hold time 0ns? I'm guessing not. I don't know why they even give setup/hold times anymore, since PLLs/delay chains allow you to shift to about any setup time you want(but always at the expense of hold).
For 3Gbps, you would need to use the high-speed transceivers. For 1.6Gbps down to approximately 900Mbps, you can use LVDS with DPA. For 900Mbps downto 500MBps, straight LVDS should work. For below 500Mbps, regular I/O using DDR registers should work. Those are really rough figures off the top-of-my-head, and dependent on I/O standard, board layout, speed grade, the other device being connected to, etc., but hopefully in the right ballpark.